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DATA SHEET
PCF8562 Universal LCD driver for low multiplex rates
Preliminary Specification November 22, 2004
Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
CONTENTS 1 2 3 4 5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 12 13 14 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Power-on reset LCD bias generator LCD voltage selector LCD drive mode waveforms Oscillator Timing Display register Segment outputs Backplane outputs Display RAM Data pointer Device Select Output bank selector Input bank selector Blinker CHARACTERISTICS OF THE I2C-BUS Bit transfer Start and stop conditions System configuration Acknowledge PCF8562 I2C-bus controller Input filters I2C-bus protocol Command decoder Display controller Multiple chip operation LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS DEVICE PROTECTION PACKAGE OUTLINES SOLDERING 14.1 14.2 14.3 14.4 14.5 15 16 17 18
PCF8562
Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
November 22, 2004
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
1 FEATURES
PCF8562
* Single-chip LCD controller/driver * Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing * Selectable display bias configuration: static, 1/2 and 1/3 * Internal LCD bias generation with voltage-follower buffers * 32 segment drives: up to sixteen 8-segment numeric characters; up to eight 15-segment alphanumeric characters; or any graphics of up to 128 elements * 32 x 4-bit RAM for display data storage * Auto-incremental display data loading across device subaddress boundaries * Display memory bank switching in static and duplex drive modes * Versatile blinking modes * Independent supplies possible for LCD and logic voltages * Wide power supply range: from 1.8 to 5.5 V * Wide logic LCD supply range: from 2.5 V for low-threshold LCDs and up to 6.5 V for guest-host LCDs and high-threshold (automobile) twisted nematic LCDs * Low power consumption * 400 kHz I2C-bus interface * TTL/CMOS compatible * Compatible with 4, 8 or 16-bit microprocessors or microcontrollers * No external components * Compatible with chip-on-glass technology * Manufactured in silicon gate CMOS process. 2 GENERAL DESCRIPTION
The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 32 segments. The PCF8562 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremental addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8562TT TSSOP48 plastic, 48 leads; body DESCRIPTION VERSION SOT362-1
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Universal LCD driver for low multiplex rates PCF8562
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
5 PINNING PIN SYMBOL PCF8562TT SDA SCL CLK VDD SYNC OSC A0 to A2 SAO VSS VLCD BP0 to BP3 S0 to S22 S23 to S31 10 11 13 14 12 15 16 to 18 19 20 21 22 to 25 26 to 48 1 to 9 I2C-bus serial data Input / Output I2C-bus serial clock input external clock input / output supply voltage cascade synchronisation input / output internal oscillator enable input sub address inputs I2C-bus slave address input: bit 0 logic ground LCD supply voltage LCD backplane outputs LCD segments output DESCRIPTION
PCF8562
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
PCF8562
48
1
S23 S24 S25 S26 S27 S28 S29 S30 S31 SDA SCL SYNC CLK VDD OSC A0 A1 A2 SA0 V SS VLCD BP0 BP2 BP1
25 24
S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12
PCF8562
S11 S10 S9 S8 S7 S6 S5 S4 S3
MDB073v2
S2 S1 S0 BP3
Fig.2 Pin Configuration (TSSOP48)
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
6 FUNCTIONAL DESCRIPTION
PCF8562
The PCF8562 is a versatile peripheral device designed to interface any microprocessor/microcontroller with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 32 segments. The display configurations possible with the PCF8562 depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 1; all of these configurations can be implemented in the typical system shown in Fig.4. The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8562. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application. Table 1 Selection of display configurations NUMBER OF BACKPLANE S 4 3 2 1 SEGMENTS 128 86 64 32 7-SEGMENTS NUMERIC DIGITS 16 12 8 4 INDICATOR SYMBOLS 16 12 8 4 14-SEGMENTS ALPHANUMERIC DOT MATRIX CHARACTERS 8 6 4 2 INDICATOR SYMBOLS 16 12 8 4 128 dots (4 x 32) 96 dots (3 x 32) 64 dots (2 x 32) 32 dots (1 x 32)
VDD R
tr 2CB SDA SCL OSC
VDD
VLCD
32 segment drives
HOST MICROPROCESSOR/ MICROCONTROLLER
LCD PANEL (up to 128 elements)
PCF8562
4 backplanes
A0 VSS
A1
A2
SA0 VSS
MDB079v2
The resistance of the power supply lines must be kept to a minimum.
Fig.4 Typical system configuration.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
6.1 Power-on reset
PCF8562
At power-on the PCF8562 resets to the following starting conditions: * All backplane outputs are set to VLCD * All segment outputs are set to VLCD * Drive mode `1 : 4 multiplex with 13bias' is selected * Blinking is switched off * Input and output bank selectors are reset (as defined in Table 4) * The I2C-bus interface is initialized * The data pointer and the subaddress counter are cleared * Display is disabled. Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action. 6.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising three resistors connected in series between VLCD and VSS. The middle resistor can be bypassed to provide a 12bias voltage level for the 1 : 2 multiplex configuration. The LCD voltage can be temperature compensated externally via the supply to pin VLCD. 6.3 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting Discrimination ratios (D), are given in Table 2. A practical value for VLCD is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1 : 3 and 1 : 4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller. 6.3.1 LCD BIAS FORMULAE
1 Bias is calculated by the formula -----------1+a where for 12 bias, a = 1; for 13 bias, a = 2.
2 1 1 --- + ( N - 1 ) ------------ 1 + a N -----------------------------------------------------------N
The LCD on voltage (Von) is calculated by the formula
V op
The LCD off voltage (Voff) is calculated by the formula
V op
a - ( 2a + N ) ---------------------------------2 N (1 + a)
2
where Vop is the resultant voltage at the LCD segment; N is the LCD drive mode: 1 = static, 2 = 1 : 2, 3 = 1 : 3, 4 = 1 : 4.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
V on Discrimination is the ratio of Von to Voff, and is determined by the formula --------- = V off (a + 1) + (N - 1) -------------------------------------------2 (a - 1) + (N - 1)
2
PCF8562
Using the above formula, the discrimination for an LCD drive mode of 1 : 3 with 12bias is 21 discrimination for an LCD drive mode of 1 : 4 with 12bias is ---------- = 1.528. 3
3 = 1.732, and the
The advantage of these LCD drive modes is a reduction of the LCD full-scale voltage VLCD as follows: * 1 : 3 multiplex (12 bias): VLCD = 6 x V off(rms) = 2.449 Voff(rms)
* 1 : 4 multiplex (12 bias): VLCD =
(4 x 3) --------------------3
= 2.309 Voff(rms)
These compare with VLCD = 3 Voff(rms) when 13 bias is used. Table 2 Discrimination ratios NUMBER OF LCD DRIVE MODE BACKPLANES static 1 : 2 multiplex 1 : 2 multiplex 1 : 3 multiplex 1 : 4 multiplex 1 2 2 3 4 LEVELS 2 3 4 4 4 LCD BIAS CONFIGURATION static
1 2 1 3 1 3 1 3
V off(rms) -------------------V lcd 0 0.354 0.333 0.333 0.333
Von(rms) -------------------V lcd 1 0.791 0.745 0.638 0.577
V on(rms) D = -------------------V off(rms) 2.236 2.236 1.915 1.732
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
6.4 6.4.1 LCD drive mode waveforms STATIC DRIVE MODE
PCF8562
The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Fig.5.
Tframe VLCD BP0 VSS VLCD Sn VSS VLCD Sn + 1 VSS VLCD (a) Waveforms at driver. state 1 (on) state 2 (off) LCD segments
ull pagewidth
state 1
0V
-VLCD VLCD
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = V LCD V state2(t) = V S
n+1
(t) - V BP0(t)
state 2
0V
V off(rms) = 0 V
-VLCD
(b) Resultant waveforms at LCD segment.
MGL745
Fig.5 Static drive mode waveforms.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
6.4.2 1 : 2 MULTIPLEX DRIVE MODE
PCF8562
The 1 : 2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of 12bias or 13bias as shown in Figs 6 and 7.
handbook, full pagewidth
Tframe VLCD BP0 VLCD/2 VSS state 1 VLCD BP1 VLCD/2 VSS VLCD Sn VSS VLCD Sn + 1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V -VLCD/2 -VLCD VLCD VLCD/2 state 2 0V -VLCD/2 -VLCD (b) Resultant waveforms at LCD segment.
MGL746
LCD segments
state 2
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0.791V LCD V state2(t) = V S (t) - V BP1(t)
n
V off(rms) = 0.354V LCD
Fig.6 Waveforms for the 1 : 2 multiplex drive mode with 12 bias.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
PCF8562
handbook, full pagewidth
Tframe VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD Sn 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V -VLCD/3 -2VLCD/3 -VLCD (b) Resultant waveforms at LCD segment.
MGL747
LCD segments
BP0
state 1 state 2
BP1
Sn + 1
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0.745V LCD V state2(t) = V S (t) - V BP1(t)
n
V off(rms) = 0.333V LCD
Fig.7 Waveforms for the 1 : 2 multiplex drive mode with 13 bias.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
6.4.3 1 : 3 MULTIPLEX DRIVE MODE
PCF8562
When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies (see Fig.8).
handbook, full pagewidth
Tframe VLCD 2VLCD/3 VLCD/3 VSS VLCD BP1 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V -VLCD/3 -2VLCD/3 -VLCD state 1 state 2 LCD segments
BP0
BP2
Sn
Sn + 1
Sn + 2
state 1
(b) Resultant waveforms at LCD segment.
MGL748
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0638V LCD V state2(t) = V S (t) - V BP1(t)
n
V off(rms) = 0.333V LCD
Fig.8 Waveforms for the 1 : 3 multiplex drive mode.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
6.4.4 1 : 4 MULTIPLEX DRIVE MODE
PCF8562
When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies (see Fig.9).
handbook, full pagewidth
Tframe VLCD 2VLCD/3 VLCD/3 VSS VLCD state 1 state 2 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 LCD segments
BP0
BP1
BP2
BP3
Sn
Sn + 1
Sn + 2
Sn + 3
state 1
0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0577V LCD V state2(t) = V S (t) - V BP1(t)
n
state 2
0V -VLCD/3 -2VLCD/3 -VLCD
V off(rms) = 0.333V LCD
(b) Resultant waveforms at LCD segment.
MGL749
Fig.9 Waveforms for the 1 : 4 multiplex drive mode.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
6.5 6.5.1 Oscillator INTERNAL CLOCK
PCF8562
The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. After power-up, pin SDA must be HIGH to guarantee that the clock starts. 6.5.2 EXTERNAL CLOCK
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame signal frequency is determined by the clock frequency (fCLK). A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state. 6.6 Timing
The PCF8562 timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division integer of the clock frequency (nominally 64 kHz) from either the internal or an external clock. f CLK Frame frequency = --------24 6.7 Display register
The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and each column of the display RAM. 6.8 Segment outputs
The LCD drive section includes 32 segment outputs S0 to S31 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display latch. When less than 32 segment outputs are required, the unused segment outputs should be left open-circuit. 6.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which should be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. In the 1 : 3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1 : 2 multiplex drive mode, BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 6.10 Display RAM
The display RAM is a static 32 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on-state of the corresponding LCD segment; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 32 segments operated with respect to backplane BP0 (see Fig.10). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively. When display data is transmitted to the PCF8562, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. For example, in the 1 : 2 mode, the RAM data is stored every second bit. To illustrate the filling order, an example of a November 22, 2004 15
Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
PCF8562
7-segment numeric display showing all drive modes is given in Fig.10; the RAM filling organization depicted applies equally to other LCD types.
display RAM addresses (rows) / segment outputs (S) 0 0 display RAM bits 1 (columns) / backplane outputs 2 (BP) 3
MBE525v2
1
2
3
4
27
28
29
30
31
Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs also between bits in a RAM word and the backplane outputs.
With reference to Fig.10, in the static drive mode, the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1 : 2 mode, the eight transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses. In the 1 : 3 mode, these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. In the 1 : 4 mode, the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses. 6.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte is stored at the display RAM address indicated by the data pointer in accordance with the filling order shown in Fig.11. After each byte is stored, the contents of the data pointer are automatically incremented by a value dependent on the selected LCD drive mode: eight (static drive mode), four (1 : 2 mode), three (1 : 3 mode) or two (1 : 4 mode). If an I2C-bus data access is terminated early then the state of the data pointer will be unknown. The data pointer should be re-written prior to further RAM accesses. 6.12 Device Select
Storage is allowed to take place when the internal select register agrees with the hardware subaddress applied to A0, A1 and A2. The hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface. 6.13 Output bank selector
The output bank selector selects one of the four bits per display RAM address for transfer to the display latch. The actual bit chosen depends on the selected LCD drive mode and on the instant in the multiplex sequence. In 1 : 4 mode, all RAM addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 mode, bits 0, 1 and 2 are selected sequentially. In 1 : 2 mode, bits 0 and 1 are selected and, in static mode, bit 0 is selected. Signal SYNC will reset these sequences to the following starting points; bit 3 for 1 : 4 mode, bit 2 for 1 : 3 mode, bit 1 for 1 : 2 mode and bit 0 for static mode.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
PCF8562
The PCF8562 includes a RAM bank switching feature in the static and 1 : 2 drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In 1 : 2 mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This allows display information to be prepared in an alternative bank and then selected for display when it is assembled. 6.14 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. The BANK SELECT command can be used to load display data in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 mode. The input bank selector functions are independent of the output bank selector. 6.15 Blinker
The PCF8562 has a very versatile display blinking capability. The whole display can blink at a frequency selected by the BLINK command. Each blink frequency is a multiple integer value of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected, as shown in Table 3. An additional feature allows an arbitrary selection of LCD segments to be blinked in the static and 1 : 2 drive modes. This is implemented without any communication overheads by the output bank selector which alternates the displayed data between the data in the display RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can also be implemented by the BLINK command. In the 1 : 3 and 1 : 4 drive modes, where no alternative RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. The entire display can be blinked at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit E at the required rate using the MODE SET command. Table 3 Blinking frequencies BLINK MODE Off 2 Hz NORMAL OPERATING MODE RATIO - f CLK ---------768 f CLK -----------1536 f CLK -----------3072 NOMINAL BLINK FREQUENCY blinking off 2 Hz
1 Hz 0.5 Hz
1 Hz 0.5 Hz
Note 1. Blink modes 0.5, 1 and 2 Hz, and nominal blink frequencies 0.5, 1 and 2 Hz correspond to an oscillator frequency (fCLK) of 1536 Hz at pin CLK. The oscillator frequency range is given in Chapter 11.
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1:3 multiplex 1:4 multiplex
Sn 1
Philips Semiconductors
Universal LCD driver for low multiplex rates
drive mode
LCD segments
a f g e d Sn 6 c b Sn Sn Sn 7 DP 1
LCD backplanes
display RAM filling order
transmitted display byte
Sn Sn Sn
2 3 4 5
BP0
n bit/ BP 0 1 2 3 c x x x
n1 b x x x
n2 a x x x
n3 f x x x
n4 g x x x
n5 e x x x
n6 d x x x
n7 MSB DP x x x cbaf LSB g e d DP
static
Sn
Sn
BP0 a f g b
n bit/ BP
BP1 c
n1 f g x x
n2 e c x x
n3 d DP x x MSB abf LSB g e c d DP
1:2
Sn
1
multiplex
Sn Sn Sn Sn
2 3
e d
DP
0 1 2 3
a b x x
1 2 f
a b g e d c DP Sn
BP0
n bit/ BP
BP1 BP2
n1 a d g x
n2 f e x x MSB b DP c a d g f LSB e
0 1 2 3
b DP c x
Sn f
a b g e d c DP BP1 BP3 BP0 BP2
n bit/ BP 0 1 2 3 a c b DP
n1 f e g d
MSB a c b DP f
LSB egd
Preliminary specification
handbook, full pagewidth
MGL751
PCF8562
x = data bit unchanged.
Fig.11 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.
Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
7 CHARACTERISTICS OF THE I2C-BUS
PCF8562
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. In chip-on-glass applications where the track resistance from the SDA pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is therefore necessary to minimize the track resistance from the SDA pad to the system SDA line to guarantee a valid LOW-level during the acknowledge cycle. 7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.12). 7.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P), (see Fig.13). 7.3 System configuration
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves', (see Fig.14). 7.4 Acknowledge
The number of data bytes that can be transferred from transmitter to receiver between the START and STOP conditions is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted by the transmitter during which time the master generates an extra acknowledge related clock pulse. An addressed slave receiver must generate an acknowledge after receiving each byte. Also a master receiver must generate an acknowledge after receiving each byte that has been clocked out of the slave transmitter. The acknowledging device must pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.15). 7.5 PCF8562 I2C-bus controller
The PCF8562 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8562 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. 7.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.7 I2C-bus protocol I2C-bus
Two slave addresses (01110000 and 01110010) are reserved for the PCF8562. The least significant bit of the slave address that a PCF8562 will respond to is defined by the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to a read access.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
PCF8562
The I2C-bus protocol is shown in Fig.16. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCF8562 slave addresses available. All PCF8562s whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored by all PCF8562s whose SA0 inputs are set to the alternative level. After an acknowledgement, one or more command bytes follow which define the status of the PCF8562. The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see Fig.17). The command bytes are also acknowledged by all addressed PCF8562s on the bus. After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated. An acknowledgement after each byte is asserted only by PCF8562s that are addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master asserts a STOP condition (P). Alternately a START may be asserted to RESTART an I2C-bus access. 7.8 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation bit C in their most significant bit position as shown in Fig.17. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data. The five commands available to the PCF8562 are defined in Table 4.
SDA
SCL data line stable; data valid change of data allowed
MBA607
Fig.12 Bit transfer.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
PCF8562
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.13 Definition of START and STOP conditions.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.14 System configuration.
dbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.15 Acknowledgement on the I2C-bus.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
PCF8562
handbook, full pagewidth
acknowledge R/W slave address S 011100A0AC 0 1 byte acknowledge
S
COMMAND
A
DISPLAY DATA
A
P
n 1 byte(s)
n 0 byte(s) update data pointers
MDB078v2
Fig.16 I2C-bus protocol.
MSB C
C = 0 = last command. C = 1 = commands continue.
LSB REST OF OPCODE
MSA833
Fig.17 Format of command byte.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
Table 4 Definition of PCF8562 commands OPCODE C 1 0
(1)
PCF8562
COMMAND MODE SET
OPTIONS B M1 M0 Table 5 Table 6 Table 7
DESCRIPTION Defines LCD drive mode. Defines LCD bias configuration. Defines display status; the possibility to disable the display allows implementation of blinking under external control. Six bits of immediate data, bits P5 to P0, are transferred to the data pointer to define one of 32 display RAM addresses. Three bits of immediate data, bits A0 to A2, are transferred to the subaddress counter to define one of eight hardware subaddresses. Defines input bank selection (storage of arriving display data). Defines output bank selection (retrieval of LCD display data); the BANK SELECT command has no effect in 1 : 3 and 1 : 4 multiplex drive modes. Defines the blink frequency. Selects the blink mode; normal operation with frequency set by BF1, BF0 or blinking by alternating display RAM banks; alternating RAM bank blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes.
E
LOAD DATA POINTER DEVICE SELECT
C
0
P5
P4
P3
P2
P1
P0
Table 8
C
1
1
0
0
A2
A1
A0
Table 9
BANK SELECT
C
1
1
1
1
0
I
O
Table 10 Table 11
BLINK
C
1
1
1
0
A
BF1 BF0 Table 12 Table 13
Note 1. Not used.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
Table 5 Mode set option 1 LCD DRIVE MODE DRIVE MODE Static 1:2 1:3 1:4 Table 6 BP0 BP0, BP1 BP0, BP1, BP2 BP0, BP1, BP2, BP3 Mode set option 2 LCD BIAS 13bias 12bias Table 7 Mode set option 3 DISPLAY STATUS Disabled (blank) Enabled Table 8 Load data pointer option 1 BITS BIT E 0 1 BIT B 0 1 BACKPLANE M1 0 1 1 0 BITS M0 1 0 1 0
PCF8562
DESCRIPTION
6 bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0 Table 9 Device select option 1 BITS A2 A1 A0
DESCRIPTION 3 bit binary value of 0 to 7
Table 10 Bank select option 1 (input) MODE BIT I STATIC RAM bit 0 RAM bit 2 1:2 RAM bits 0 and 1 RAM bits 2 and 3 0 1
Table 11 Bank select option 2 (output) MODE BIT O STATIC RAM bit 0 RAM bit 2 1:2 RAM bits 0 and 1 RAM bits 2 and 3 0 1
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
Table 12 Blink option 1 BITS BLINK FREQUENCY BF1 Off 2 Hz 1 Hz 0.5 Hz Table 13 Blink option 2 BLINK MODE Normal blinking Alternate RAM bank blinking Note 1. Normal blinking is assumed when LCD multiplex drive modes 1 : 3 or 1 : 4 are selected. 7.9 Display controller BIT A 0 1 0 0 1 1 BF0 0 1 0 1
PCF8562
The display controller executes the commands identified by the command decoder. It contains the device's status registers and co-ordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. 7.10 Multiple chip operation
For large display configurations please refer to the PCF8576D device. Please refer to PCF8576D if you need to drive more segments (>128 elements).
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
Table 14 SYNC contact resistance NUMBER OF DEVICES 2 3 to 5 6 to 10 10 to 16 MAXIMUM CONTACT RESISTANCE 6 000 2 200 1 200 700
PCF8562
The contact resistance between the SYNC input/output on each cascaded device must be controlled. If the resistance is too high, the device will not be able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 14. 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD VLCD Vi1 Vi2 VO II IO IDD ISS ILCD Ptot PO Tstg 9 supply voltage LCD supply voltage input voltage CLK, SYNC, SA0, OSC, A0 to A2 input voltage SCL and SDA output voltage S0 to S39, BP0 to BP3 DC input current DC output current VDD current VSS current VLCD current total power dissipation power dissipation per output storage temperature PARAMETER MIN. -0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 -10 -10 -50 -50 -50 - - -65 MAX. +6.5 +7.5 VDD + 0.5 +6.5 VDD + 0.5 +10 +10 +50 +50 +50 400 100 +150 V V V V V mA mA mA mA mA mW mW C UNIT
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices" ).
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Preliminary specification
Universal LCD driver for low multiplex rates
10 DC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD VLCD IDD ILCD Logic VIL VIH VIL2 VIH2 IOL1 IOH1 IOL2 IL1 IL2 VPOR CI VBP VS RBP RS Notes 1. VLCD > 3 V for 13bias. LOW-level input voltage CLK, SYNC, OSC, A0 to A2 and SA0 HIGH-level input voltage CLK, SYNC, OSC, A0 to A2 and SA0 LOW-level input voltage SCL, SDA HIGH-level input voltage SCL, SDA HIGH-level output current CLK LOW-level output current SDA leakage current CLK, SCL, SDA, A0 to A2 and SA0 leakage current OSC power-on reset voltage level input capacitance note 4 note 3 VOH = 4.6 V; VDD = 5 V VOL = 0.4 V; VDD = 5 V VI = VDD or VSS VI = VDD LOW-level output current CLK, SYNC VOL = 0.4 V; VDD = 5 V VSS 0.7VDD VSS 0.7VDD 1 -1 3 -1 -1 1.0 - -100 -100 note 5; VLCD = 5 V note 5; VLCD = 5 V - - - - - - - - - - - 1.3 - - - 1.5 6.0 supply voltage LCD supply voltage supply current LCD supply current note 1 note 2; fCLK = 1 536 Hz note 2; fCLK = 1 536 Hz 1.8 2.5 - - - - 8 24 PARAMETER CONDITIONS MIN. TYP.
PCF8562
MAX.
UNIT
5.5 6.5 20 60
V V A A V V V V mA mA mA A A V pF
0.3VDD VDD 0.3VDD VDD - - - +1 +1 1.6 7 +100 +100
LCD outputs DC voltage tolerance BP0 to BP3 DC voltage tolerance S0 to S31 output resistance BP0 to BP3 output resistance S0 to S31 mV mV k k
2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive. 3. When tested, I2C pins SCL and SDA have no diode to VDD and may be driven according to the Vi2 limiting values given in Chapter 8. Also see Fig.21. 4. Periodically sampled, not 100% tested. 5. Outputs measured one at a time.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
11 AC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fCLK tCLKH tCLKL tPD(SYNC) tSYNCL tPD(LCD) PARAMETER oscillator frequency input CLK HIGH time input CLK LOW time SYNC propagation delay SYNC LOW time driver delays with test loads VLCD = 5 V; note 2 CONDITIONS note 1 MIN. 960 60 60 - 1 - - 1.3 0.6 0.6 1.3 0.6 - - - 100 0 0.6 - TYP. 1890 - - 30 - - - - - - - - - - - - - - -
PCF8562
MAX. 2640 - - - - 30
UNIT Hz s s ns s s
Timing characteristics: I2C-bus; note 3 fSCL tBUF tHD;STA tSU;STA tLOW tHIGH tr tf CB tSU;DAT tHD;DAT tSU;STO tSW Notes 1. Typical output duty factor: 50% measured at the CLK output pin. 2. Not tested in production. 3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. SCL clock frequency bus free time between a STOP and START START condition hold time set-up time for a repeated START condition SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time capacitive bus line load data set-up time data hold time set-up time for STOP condition tolerable spike width on bus 400 - - - - - 0.3 0.3 400 - - - 50 kHz s s s s s s s pF ns ns s ns
handbook, full pagewidth
SYNC
6.8 (2%) 3.3 k (2%)
VDD
CLK
0.5VDD
SDA, SCL
1.5 k (2%)
VDD
BP0to BP and 3, S0to S31
1 nF VSS
MCE439v2
Fig.18 Test loads.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
PCF8562
handbook, full pagewidth
1/fCLK tCLKH tCLKL 0.7VDD 0.3VDD
CLK
SYNC
0.7VDD 0.3VDD tPD(SYNC) tSYNCL tPD(SYNC)
BP0 to BP3, and S0 to S31
0.5 V (VDD = 5 V) 0.5 V tPD(LCD)
MCE424v2
Fig.19 Driver timing waveforms.
handbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t
HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t SU;STO
Fig.20 I2C-bus timing waveforms.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
12 DEVICE PROTECTION
PCF8562
handbook, full pagewidth
VDD SA0
VDD
VSS VDD CLK
VSS
SCL VSS VDD VSS OSC
VSS VDD SYNC SDA
VSS VDD A0, A1 A2
VSS
VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD S0 to S31 VSS
MDB076
VLCD
VSS
Fig.21 Device protection diagram.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
13 PACKAGE OUTLINES
PCF8562
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-10 99-12-27
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Preliminary specification
Universal LCD driver for low multiplex rates
14 SOLDERING 14.1 Introduction to soldering surface mount packages
PCF8562
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 220 C (SnPb process) or below 245 C (Pb-free process) - for all the BGA packages - for packages with a thickness S 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. November 22, 2004 32
Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
14.4 Manual soldering
PCF8562
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 14.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP Notes 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not suitable(3) suitable not recommended(4)(5) not recommended(6) SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
15 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
PCF8562
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
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Philips Semiconductors
Preliminary specification
Universal LCD driver for low multiplex rates
17 DISCLAIMERS
PCF8562
Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
November 22, 2004
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands

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